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P89LPC9201/9211/922A1/9241/ 9251
8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC
Rev. 01 -- 16 April 2009 Preliminary data sheet
1. General description
The P89LPC9201/9211/922A1/9241/9251 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the device in order to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
I 2 kB/4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory. I 4-input multiplexed 8-bit ADC/single DAC output (P89LPC9241/9251). Two analog comparators with selectable inputs and reference source. I On-chip temperature sensor integrated with ADC module (P89LPC9241/9251). I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output). I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. I Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. I 20-pin TSSOP and DIP packages with 15 I/O pins minimum and up to 18 I/O pins while using on-chip oscillator and reset options.
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. I Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. I In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to 5 %, requiring no external components. The watchdog prescaler is selectable from eight values. I High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. I Clock switching on the fly among internal RC oscillator, watchdog oscillator, external clock source provides optimal support of minimal power active mode with fast switching to maximum performance. I Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). I Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. I Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. I Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6, P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. I Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC9201/9211/922A1/9241/9251 when internal reset option is selected. I Four interrupt priority levels. I Eight keypad interrupt inputs, plus two additional external interrupt inputs. I Schmitt trigger port inputs. I Second data pointer. I Emulation support.
P89LPC92X1_1 (c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
3. Ordering information
Table 1. Ordering information Package Name P89LPC9201FDH P89LPC9211FDH P89LPC922A1FDH P89LPC922A1FN P89LPC9241FDH P89LPC9251FDH TSSOP20 TSSOP20 TSSOP20 DIP20 TSSOP20 TSSOP20 Description plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line package; 20 leads (300 mil) plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT360-1 SOT360-1 SOT360-1 SOT146-1 SOT360-1 SOT360-1 Type number
3.1 Ordering options
Table 2. Ordering options Flash memory 2 kB 4 kB 8 kB 8 kB 4 kB 8 kB Temperature range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz Type number P89LPC9201FDH P89LPC9211FDH P89LPC922A1FDH P89LPC922A1FN P89LPC9241FDH P89LPC9251FDH
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
4. Block diagram
P89LPC9201/9211/922A1
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
2 kB/4 kB/8 kB CODE FLASH 256-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os internal bus
UART REAL-TIME CLOCK/ SYSTEM TIMER
TXD RXD
P3[1:0]
I2C-BUS
SCL SDA
P1[7:0]
WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 T0 T1 CMP2 CIN2B CMP1 CIN1B
P0[7:0]
KEYPAD INTERRUPT
ANALOG COMPARATORS
CIN2A CIN1A
PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 CRYSTAL OR RESONATOR XTAL2 CONFIGURABLE OSCILLATOR
CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aae421
Fig 1.
Block diagram (P89LPC9201/9211/922A1)
P89LPC92X1_1
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Preliminary data sheet
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
P89LPC9241/9251
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
4 kB/8 kB CODE FLASH 256-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os internal bus
UART REAL-TIME CLOCK/ SYSTEM TIMER
TXD RXD
P3[1:0]
I2C-BUS
SCL SDA
P1[7:0]
WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 T0 T1 CMP2 CIN2B CMP1 CIN1B
P0[7:0]
KEYPAD INTERRUPT
ANALOG COMPARATORS
CIN2A CIN1A AD10 AD11 AD12 AD13 DAC1
PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 CRYSTAL OR RESONATOR XTAL2 CONFIGURABLE OSCILLATOR
CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER
ADC1/DAC1 (TEMPERATURE SENSOR)
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aae422
Fig 2.
Block diagram (P89LPC9241/9251)
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
5. Functional diagram
VDD VSS
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
P89LPC9201/ 9211/922A1
TXD RXD T0 INT0 INT1 RST
SCL SDA
PORT 3 XTAL1
002aae423
Fig 3.
Functional diagram (P89LPC9201/9211/922A1)
VDD
VSS
DAC1
AD10 AD11 AD12 AD13
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
P89LPC9241/ 9251
TXD RXD T0 INT0 INT1 RST
SCL SDA
PORT 3 XTAL1
002aae424
Fig 4.
Functional diagram (P89LPC9241/9251)
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
6. Pinning information
6.1 Pinning
P0.0/CMP2/KBI0 P1.7 P1.6 P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA
1 2 3 4 5 6 7 8 9
20 P0.1/CIN2B/KBI1/AD10 19 P0.2/CIN2A/KBI2/AD11 18 P0.3/CIN1B/KBI3/AD12 17 P0.4/CIN1A/KBI4/AD13/DAC1 16 P0.5/CMPREF/KBI5 15 VDD 14 P0.6/CMP1/KBI6 13 P0.7/T1/KBI7 12 P1.0/TXD 11 P1.1/RXD
002aae425
P89LPC9241/9251
P1.2/T0/SCL 10
Fig 5.
P89LPC9241/9251 TSSOP20 pin configuration
P0.0/CMP2/KBI0 P1.7 P1.6 P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA
1 2 3 4 5 6 7 8 9
20 P0.1/CIN2B/KBI1 19 P0.2/CIN2A/KBI2 18 P0.3/CIN1B/KBI3 17 P0.4/CIN1A/KBI4 16 P0.5/CMPREF/KBI5 15 VDD 14 P0.6/CMP1/KBI6 13 P0.7/T1/KBI7 12 P1.0/TXD 11 P1.1/RXD
002aae426
P89LPC9201/9211/ 922A1
P1.2/T0/SCL 10
Fig 6.
P89LPC9201/9211/922A1 TSSOP20 pin configuration
P89LPC92X1_1
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
P89LPC922A1
P0.0/CMP2/KBI0 P1.7 P1.6 P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA 1 2 3 4 5 6 7 8 9 20 P0.1/CIN2B/KBI1 19 P0.2/CIN2A/KBI2 18 P0.3/CIN1B/KBI3 17 P0.4/CIN1A/KBI4 16 P0.5/CMPREF/KBI5 15 VDD 14 P0.6/CMP1/KBI6 13 P0.7/T1/KBI7 12 P1.0/TXD 11 P1.1/RXD
002aae427
P1.2/T0/SCL 10
Fig 7.
P89LPC922A1 DIP20 pin configuration
P89LPC92X1_1
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
6.2 Pin description
Table 3. Symbol Pin description Pin TSSOP20, DIP20 P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/ KBI0 1 I/O O I P0.1/CIN2B/ KBI1/AD10 20 I/O I I I P0.2/CIN2A/ KBI2/AD11 19 I/O I I I P0.3/CIN1B/ KBI3/AD12 18 I/O I I I P0.4/CIN1A/ KBI4/DAC1/AD13 17 I/O I I O I P0.5/CMPREF/ KBI5 16 I/O I I P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output KBI0 -- Keyboard input 0. P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD10 -- ADC1 channel 0 analog input. (P89LPC9241/9251) P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD11 -- ADC1 channel 1 analog input. (P89LPC9241/9251) P0.3 -- Port 0 bit 3. High current source. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD12 -- ADC1 channel 2 analog input. (P89LPC9241/9251) P0.4 -- Port 0 bit 4. High current source. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. DAC1 -- Digital-to-analog converter output 1. (P89LPC9241/9251) AD13 -- ADC1 channel 3 analog input. (P89LPC9241/9251) P0.5 -- Port 0 bit 5. High current source. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. Type Description
P89LPC92X1_1
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
Table 3. Symbol
Pin description ...continued Pin TSSOP20, DIP20 Type Description
P0.6/CMP1/KBI6
14
I/O O I
P0.6 -- Port 0 bit 6. High current source. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. P0.7 -- Port 0 bit 7. High current source. T1 -- Timer/counter 1 external count input or overflow output. KBI7 -- Keyboard input 7.
P0.7/T1/KBI7
13
I/O I/O I
P1.0 to P1.7
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for [1] three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt trigger inputs. Port 1 also provides various special functions as described below:
P1.0/TXD P1.1/RXD P1.2/T0/SCL
12 11 10
I/O O I/O I I/O I/O I/O
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C-bus serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C-bus serial data input/output. P1.4 -- Port 1 bit 4. High current source. INT1 -- External interrupt 1 input. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. P1.6 -- Port 1 bit 6. High current source. P1.7 -- Port 1 bit 7. High current source. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. All pins have Schmitt trigger inputs. Port 3 also provides various special functions as described below:
P1.3/INT0/SDA
9
I/O I I/O
P1.4/INT1 P1.5/RST
8 4
I/O I I I
P1.6 P1.7 P3.0 to P3.1
3 2
I/O I/O I/O
P89LPC92X1_1
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
Table 3. Symbol
Pin description ...continued Pin TSSOP20, DIP20 Type Description
P3.0/XTAL2/ CLKOUT
7
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P3.1/XTAL1
6
I/O I
VSS VDD
5 15
I I
[1]
Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC92X1_1
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
7. Functional description
Remark: Please refer to the P89LPC9201/9211/922A1/9241/9251 User manual for a more detailed functional description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 16 April 2009
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Preliminary data sheet Rev. 01 -- 16 April 2009
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Table 4. Special function registers - P89LPC9201/9211/922A1 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB E7 CLKLP E6 EBRR E5 ENT1 E4 ENT0 E3 SRST E2 0 E1 E0H A2H DPS Reset value LSB E0 00 00 0000 0000 0000 00x0 Hex Binary
Bit address ACC* AUXR1 Accumulator Auxiliary function register B register Baud rate generator 0 rate low Baud rate generator 0 rate high Baud rate generator 0 control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low 83H 82H E7H E6H
Bit address B* BRGR0[2] F0H BEH
F7
F6
F5
F4
F3
F2
F1
F0 00 00 0000 0000 0000 0000
P89LPC9201/9211/922A1/9241/9251
BRGR1[2]
BFH
00
0000 0000
BRGCON
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[2]
xxxx xx00
CMP1 CMP2 DIVM
ACH ADH 95H
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00[1] 00[1] 00
xx00 0000 xx00 0000 0000 0000
8-bit microcontroller with 8-bit ADC
DPTR DPH DPL FMADRH FMADRL
00 00 00 00
0000 0000 0000 0000 0000 0000 0000 0000
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Table 4. Special function registers - P89LPC9201/9211/922A1 * indicates SFRs that are bit addressable. Name FMCON Description Program flash control (Read) Program flash control (Write) FMDATA I2ADR Program flash data I2C-bus slave address register I2C-bus register I2DAT I2SCLH I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 DAH DDH 00 0000 0000 control SFR Bit functions and addresses addr. MSB E4H E4H E5H DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC BUSY FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 HVA FMCMD.3 HVE FMCMD.2 SV FMCMD.1 Reset value LSB OI FMCMD.0 00 00 0000 0000 0000 0000 Hex 70 Binary 0111 0000
Preliminary data sheet Rev. 01 -- 16 April 2009
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P89LPC9201/9211/922A1/9241/9251
Bit address I2CON* D8H
DF -
DE I2EN
DD STA
DC STO
DB SI
DA AA
D9 -
D8 CRSEL 00 x000 00x0
I2SCLL
DCH
00
0000 0000
8-bit microcontroller with 8-bit ADC
I2STAT
D9H
STA.4 AF EA EF BF -
STA.3 AE EWDRT EE EST BE PWDRT
STA.2 AD EBO ED BD PBO
STA.1 AC ES/ESR EC BC PS/PSR
STA.0 AB ET1 EB BB PT1
0 AA EX1 EA EC BA PX1
0 A9 ET0 E9 EKBI B9 PT0
0 A8 EX0 E8 EI2C B8 PX0
F8
1111 1000
Bit address IEN0* A8H Bit address IEN1* E8H Bit address IP0* B8H
00
0000 0000
00[1]
00x0 0000
00[1]
x000 0000
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Table 4. Special function registers - P89LPC9201/9211/922A1 * indicates SFRs that are bit addressable. Name IP0H Description Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 SFR Bit functions and addresses addr. MSB B7H FF PWDRTH FE PST PSTH PBOH FD PSH/ PSRH FC PT1H FB PX1H FA PC PCH PT0H F9 PKBI PKBIH PATN _SEL Reset value LSB PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 00x0 0000 00x0 0000 xxxx xx00 Hex 00[1] Binary x000 0000
Preliminary data sheet Rev. 01 -- 16 April 2009
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Bit address IP1* IP1H KBCON KBMASK F8H F7H 94H 86H
P89LPC9201/9211/922A1/9241/9251
0000 0000
KBPATN
93H 87 T1/KB7 97 B7 (P0M1.7) (P0M2.7) (P1M1.7) (P1M2.7) 86 CMP1 /KB6 96 B6 (P0M1.6) (P0M2.6) (P1M1.6) (P1M2.6) 85 CMPREF /KB5 95 RST B5 (P0M1.5) (P0M2.5) 84 CIN1A /KB4 94 INT1 B4 (P0M1.4) (P0M2.4) (P1M1.4) (P1M2.4) 83 CIN1B /KB3 93 INT0/SDA B3 (P0M1.3) (P0M2.3) (P1M1.3) (P1M2.3) 82 CIN2A /KB2 92 T0/SCL B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) 81 CIN2B /KB1 91 RXD B1 XTAL1 (P0M1.1) (P0M2.1) (P1M1.1) (P1M2.1) (P3M1.1) (P3M2.1) 80 CMP2 /KB0 90 TXD B0 XTAL2 (P0M1.0) (P0M2.0) (P1M1.0) (P1M2.0) (P3M1.0) (P3M2.0)
FF
1111 1111
Bit address P0* 80H Bit address P1* P3* P0M1 P0M2 P1M1 P1M2 P3M1 P3M2 Port 1 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 3 output mode 1 Port 3 output mode 2 90H Bit address B0H 84H 85H 91H 92H B1H B2H
[1]
[1]
[1]
8-bit microcontroller with 8-bit ADC
FF[1] 00[1] D3[1] 00[1] 03[1] 00[1]
1111 1111 0000 0000 11x1 xx11 00x0 xx00 xxxx xx11 xxxx xx00
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Table 4. Special function registers - P89LPC9201/9211/922A1 * indicates SFRs that are bit addressable. Name PCON PCONA Description Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer Timer 0 and 1 auxiliary mode SFR Bit functions and addresses addr. MSB 87H B5H SMOD1 RTCPD D7 CY RTCF SMOD0 D6 AC BOIF RTCS1 VCPD D5 F0 PT0AD.5 BOF RTCS0 BOI D4 RS1 PT0AD.4 POF GF1 I2PD D3 RS0 PT0AD.3 R_BK GF0 D2 OV PT0AD.2 R_WD PMOD1 SPD D1 F1 PT0AD.1 R_SF ERTC Reset value LSB PMOD0 D0 P R_EX RTCEN 00 00
[3]
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Preliminary data sheet Rev. 01 -- 16 April 2009 16 of 74
P89LPC92X1_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
Hex 00 00[1]
Binary 0000 0000 0000 0000
Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR D0H F6H DFH D1H D2H D3H A9H
0000 0000 xx00 000x
P89LPC9201/9211/922A1/9241/9251
60[1][6] 00[6] 00[6] 00
011x xx00 0000 0000 0000 0000 0000 0000
SADEN SBUF
B9H 99H
00 xx
0000 0000
8-bit microcontroller with 8-bit ADC
xxxx xxxx
Bit address SCON* SSTAT 98H BAH
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 0000 0000 0000 0000
SP TAMOD
81H 8FH T1M2 T0M2
07 00
0000 0111 xxx0 xxx0
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Table 4. Special function registers - P89LPC9201/9211/922A1 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB 8F TF1 8E TR1 8D TF0 8C TR0 8B IE1 8A IT1 89 IE0 88H 8CH 8DH 8AH 8BH 89H 96H T1GATE RCCLK T1C/T ENCLK T1M1 TRIM.5 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 T0M1 TRIM.1 T0M0 TRIM.0 Reset value LSB 88 IT0 00 00 00 00 00 00
[5][6]
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Preliminary data sheet Rev. 01 -- 16 April 2009 17 of 74
P89LPC92X1_1 (c) NXP B.V. 2009. All rights reserved.
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Hex
Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
P89LPC9201/9211/922A1/9241/9251
WDCON WDL WFEED1 WFEED2
A7H C1H C2H C3H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4][6]
FF
1111 1111
[1] [2] [3] [4] [5] [6]
All ports are in input only (high-impedance) state after power-up.
8-bit microcontroller with 8-bit ADC
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC9201/9211/922A1 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset sources that affect these SFRs are power-on reset and watchdog reset.
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Preliminary data sheet Rev. 01 -- 16 April 2009
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NXP Semiconductors
Table 5. Name BODCFG
Extended special function registers - P89LPC9201/9211/922A1[1] Description BOD configuration register CLOCK Control register Real-time clock data register high SFR addr. FFC8H Bit functions and addresses MSB LSB BOICFG1 BOICFG0 Reset value Hex
[2]
Binary
CLKCON RTCDATH
FFDEH FFBFH
CLKOK
-
-
XTALWD
CLKDBL
FOSC2
FOSC1
FOSC0
[3]
00
0000 0000
RTCDATL
Real-time clock FFBEH data register low
00
0000 0000
P89LPC9201/9211/922A1/9241/9251
[1] [2] [3]
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.
8-bit microcontroller with 8-bit ADC
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Preliminary data sheet Rev. 01 -- 16 April 2009
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NXP Semiconductors
Table 6. Special function registers - P89LPC9241/9251 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB E7 ENBI0 ENBI1 AIN13 BNDI1 CLK2 E6 ENADCI0 ENADCI1 AIN12 BURST1 CLK1 E5 TMM0 TMM1 AIN11 SCC1 CLK0 E4 EDGE0 EDGE1 AIN10 SCAN1 INBND0 E3 ADCI0 ADCI1 AIN03 BNDI0 ENDAC1 E2 ENADC0 ENADC1 AIN02 BURST0 ENDAC0 E1 ADCS01 ADCS11 AIN01 SCC0 BSA1 E0H 8EH 97H A3H C0H A1H BBH ADCS00 ADCS10 AIN00 SCAN0 BSA0 Reset value LSB E0 00 00 00 00 00 00 FF 0000 0000 0000 0000 0000 0000 0000 0000 Hex Binary
Bit address ACC* ADCON0 ADCON1 ADINS ADMODA ADMODB AD0BH Accumulator A/D control register 0 A/D control register 1 A/D input select A/D mode register A A/D mode register B A/D_0 boundary high register A/D_0 boundary low register A/D_0 data register 0 A/D_0 data register 1 A/D_0 data register 2 A/D_0 data register 3 A/D_0 boundary high register A/D_0 boundary low register A/D_0 data register 0
P89LPC9201/9211/922A1/9241/9251
0000 0000 000x 0000 1111 1111
AD0BL
A6H
00
0000 0000
AD0DAT0 AD0DAT1 AD0DAT2 AD0DAT3 AD1BH
C5H C6H C7H F4H C4H
00 00 00 00 FF
0000 0000 0000 0000
8-bit microcontroller with 8-bit ADC
0000 0000 0000 0000 1111 1111
AD1BL
BCH
00
0000 0000
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AD1DAT0
D5H
00
0000 0000
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Table 6. Special function registers - P89LPC9241/9251 ...continued * indicates SFRs that are bit addressable. Name AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 Description A/D_0 data register 1 A/D_0 data register 2 A/D_0 data register 3 Auxiliary function register B register Baud rate generator 0 rate low Baud rate generator 0 rate high Baud rate generator 0 control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low 83H 82H 00 00 0000 0000 0000 0000 SFR Bit functions and addresses addr. MSB D6H D7H F5H A2H CLKLP EBRR ENT1 ENT0 SRST 0 DPS Reset value LSB Hex 00 00 00 00 Binary 0000 0000 0000 0000 0000 0000 0000 00x0
Preliminary data sheet Rev. 01 -- 16 April 2009
(c) NXP B.V. 2009. All rights reserved. P89LPC92X1_1
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NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
Bit address B* BRGR0[2] F0H BEH
F7
F6
F5
F4
F3
F2
F1
F0 00 00 0000 0000 0000 0000
BRGR1[2]
BFH
00
0000 0000
BRGCON
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[2]
xxxx xx00
CMP1 CMP2 DIVM
ACH ADH 95H
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00[1] 00[1] 00
xx00 0000
8-bit microcontroller with 8-bit ADC
xx00 0000 0000 0000
DPTR DPH DPL
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Table 6. Special function registers - P89LPC9241/9251 ...continued * indicates SFRs that are bit addressable. Name FMADRH FMADRL FMCON Description Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA I2ADR
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Preliminary data sheet 21 of 74
P89LPC92X1_1
NXP Semiconductors
SFR Bit functions and addresses addr. MSB E7H E6H E4H E4H E5H DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 BUSY FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 HVA FMCMD.3 HVE FMCMD.2 SV FMCMD.1
Reset value LSB Hex 00 00 OI FMCMD.0 00 GC 00 0000 0000 0000 0000 70 Binary 0000 0000 0000 0000 0111 0000
Program flash data I2C-bus slave address register I2C-bus register control
P89LPC9201/9211/922A1/9241/9251
Bit address I2CON* I2DAT I2SCLH D8H DAH DDH
DF -
DE I2EN
DD STA
DC STO
DB SI
DA AA
D9 -
D8 CRSEL 00 x000 00x0
I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register Interrupt enable 0 Interrupt enable 1
00
0000 0000
8-bit microcontroller with 8-bit ADC
I2SCLL
DCH
00
0000 0000
I2STAT
D9H
STA.4 AF EA EF EAD
STA.3 AE EWDRT EE EST
STA.2 AD EBO ED -
STA.1 AC ES/ESR EC -
STA.0 AB ET1 EB -
0 AA EX1 EA EC
0 A9 ET0 E9 EKBI
0 A8 EX0 E8 EI2C
F8
1111 1000
Bit address IEN0* A8H Bit address IEN1* E8H
00
0000 0000
00[1]
00x0 0000
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Table 6. Special function registers - P89LPC9241/9251 ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB BF FF PAD PADH BE PWDRT PWDRTH FE PST PSTH BD PBO PBOH FD BC PS/PSR PSH/ PSRH FC BB PT1 PT1H FB BA PX1 PX1H FA PC PCH B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL B8H B7H Reset value LSB B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 00x0 0000 00[1] 00[1] x000 0000 x000 0000 Hex Binary
Preliminary data sheet Rev. 01 -- 16 April 2009
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Bit address IP0* IP0H Interrupt priority 0 Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0
Bit address IP1* IP1H KBCON KBMASK F8H F7H 94H 86H
P89LPC9201/9211/922A1/9241/9251
00x0 0000 xxxx xx00 0000 0000
KBPATN
93H 87 T1/KB7 97 B7 (P0M1.7) (P0M2.7) (P1M1.7) (P1M2.7) 86 CMP1 /KB6 96 B6 (P0M1.6) (P0M2.6) (P1M1.6) (P1M2.6) 85 CMPREF /KB5 95 RST B5 (P0M1.5) (P0M2.5) 84 CIN1A /KB4 94 INT1 B4 (P0M1.4) (P0M2.4) (P1M1.4) (P1M2.4) 83 CIN1B /KB3 93 INT0/SDA B3 (P0M1.3) (P0M2.3) (P1M1.3) (P1M2.3) 82 CIN2A /KB2 92 T0/SCL B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) 81 CIN2B /KB1 91 RXD B1 XTAL1 (P0M1.1) (P0M2.1) (P1M1.1) (P1M2.1) 80 CMP2 /KB0 90 TXD B0 XTAL2 (P0M1.0) (P0M2.0) (P1M1.0) (P1M2.0)
FF
1111 1111
Bit address P0* 80H Bit address P1* P3* P0M1 P0M2 P1M1 P1M2 Port 1 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 90H Bit address B0H 84H 85H 91H 92H
[1]
8-bit microcontroller with 8-bit ADC
[1]
[1]
FF[1] 00[1] D3[1] 00[1]
1111 1111 0000 0000 11x1 xx11 00x0 xx00
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Table 6. Special function registers - P89LPC9241/9251 ...continued * indicates SFRs that are bit addressable. Name P3M1 P3M2 PCON PCONA Description Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register SFR Bit functions and addresses addr. MSB B1H B2H 87H B5H SMOD1 RTCPD D7 CY RTCF SMOD0 D6 AC BOIF RTCS1 VCPD D5 F0 PT0AD.5 BOF RTCS0 BOI ADPD D4 RS1 PT0AD.4 POF GF1 I2PD D3 RS0 PT0AD.3 R_BK GF0 D2 OV PT0AD.2 R_WD (P3M1.1) (P3M2.1) PMOD1 SPD D1 F1 PT0AD.1 R_SF ERTC Reset value LSB (P3M1.0) (P3M2.0) PMOD0 D0 P R_EX RTCEN 00 00
[3]
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Preliminary data sheet Rev. 01 -- 16 April 2009 23 of 74
P89LPC92X1_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
Hex 03[1] 00[1] 00 00[1]
Binary xxxx xx11 xxxx xx00 0000 0000 0000 0000
Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR D0H F6H DFH D1H D2H D3H A9H
P89LPC9201/9211/922A1/9241/9251
0000 0000 xx00 000x
60[1][6] 00[6] 00[6] 00
011x xx00 0000 0000 0000 0000 0000 0000
8-bit microcontroller with 8-bit ADC
SADEN SBUF
B9H 99H
00 xx
0000 0000 xxxx xxxx
Bit address SCON* SSTAT 98H BAH
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 0000 0000 0000 0000
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Table 6. Special function registers - P89LPC9241/9251 ...continued * indicates SFRs that are bit addressable. Name SP TAMOD Description Stack pointer Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2 SFR Bit functions and addresses addr. MSB 81H 8FH 8F TF1 8E TR1 8D TF0 T1M2 8C TR0 8B IE1 8A IT1 89 IE0 T0M2 88 IT0 00 00 00 00 00 T1GATE RCCLK T1C/T ENCLK T1M1 TRIM.5 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 T0M1 TRIM.1 T0M0 TRIM.0 00
[5][6]
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Preliminary data sheet Rev. 01 -- 16 April 2009 24 of 74
P89LPC92X1_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
Reset value LSB Hex 07 00 Binary 0000 0111 xxx0 xxx0
Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM 88H 8CH 8DH 8AH 8BH 89H 96H
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
P89LPC9201/9211/922A1/9241/9251
WDCON WDL WFEED1 WFEED2
A7H C1H C2H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4][6]
FF
1111 1111
8-bit microcontroller with 8-bit ADC
C3H
[1] [2] [3] [4] [5] [6]
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC9241/9251 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset sources that affect these SFRs are power-on reset and watchdog reset. CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7
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Preliminary data sheet Rev. 01 -- 16 April 2009
(c) NXP B.V. 2009. All rights reserved. P89LPC92X1_1
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Table 7. Name BODCFG
Extended special function registers - P89LPC9241/9251[1] Description BOD configuration register CLOCK Control register Temperature sensor control register Real-time clock data register high SFR addr. FFC8H Bit functions and addresses MSB LSB BOICFG1 BOICFG0 Reset value Hex
[2]
Binary
CLKCON TPSCON
FFDEH FFCAH
CLKOK -
-
-
XTALWD -
CLKDBL TSEL1
FOSC2 TSEL0
FOSC1 -
FOSC0 -
[3]
00
0000 0000
RTCDATH
FFBFH
00
0000 0000
P89LPC9201/9211/922A1/9241/9251
RTCDATL
Real-time clock FFBEH data register low
00
0000 0000
[1] [2] [3]
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.
8-bit microcontroller with 8-bit ADC
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
7.2 Enhanced CPU
The P89LPC9201/9211/922A1/9241/9251 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC9201/9211/922A1/9241/9251 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 8) and can also be optionally divided to a slower frequency (see Section 7.11 "CCLK modification: DIVM register"). Remark: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK -- Clock for the various peripheral devices and is CCLK2.
7.3.2 CPU clock (OSCCLK)
The P89LPC9201/9211/922A1/9241/9251 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.
7.4 Crystal oscillator option
The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and WDT.
7.4.1 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
7.4.2 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
7.4.3 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 16 April 2009
26 of 74
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P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
7.5 Clock output
The P89LPC9201/9211/922A1/9241/9251 supports a user-selectable clock output function on the P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9201/9211/922A1/9241/9251. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.6 On-chip RC oscillator option
The P89LPC9201/9211/922A1/9241/9251 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.7 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.
7.8 External clock input option
In this configuration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2/CLKOUT pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.9 Clock sources switch on the fly
P89LPC9201/9211/922A1/9241/9251 can implement clock source switch in any sources of watchdog oscillator, 7 MHz/14 MHz internal RC oscillator, external clock source (external crystal or external clock input) during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is `0', writing to CLKCON register is not allowed.
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XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
ADC
(P89LPC9241/9251)
OSCCLK RC OSCILLATOR WITH CLOCK DOUBLER RCCLK /2 PCLK WDT CCLK
DIVM
CPU
(7.3728 MHz/14.7456 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz 5 %) TIMER 0 AND TIMER 1
PCLK
I2C-BUS
UART
002aae428
Fig 8.
Block diagram of oscillator control
7.10 CCLK wake-up delay
The P89LPC9201/9211/922A1/9241/9251 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 s to 100 s. If the clock source is the internal RC oscillator, the delay is 200 s to 300 s. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9201/9211/922A1/9241/9251 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
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7.13 Memory organization
The various P89LPC9201/9211/922A1/9241/9251 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9201/9211/922A1/9241/9251 has 2 kB/4 kB/8 kB of on-chip Code memory.
7.14 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in Table 8.
Table 8. Type DATA IDATA On-chip data memory usages Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Size (bytes) 128 256
7.15 Interrupts
The P89LPC9201/9211/922A1/9241/9251 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC9201/9211/922A1/9241/9251 supports 12/13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, A/D Converter (P89LPC9241/9251). Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced.
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If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
7.15.1 External interrupt inputs
The P89LPC9201/9211/922A1/9241/9251 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC9201/9211/922A1/9241/9251 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.18 "Power reduction modes" for details.
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IE0 EX0 IE1 EX1 BOIF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI and RI/RI ES/ESR TI EST SI EI2C
ENADCI0(1) ADCI0(1) ENADCI1(1) ADCI1(1) ENBI0(1) BNDI0(1) ENBI1(1) BNDI1(1) EAD(1)
002aae429
wake-up (if in power-down)
interrupt to CPU
(1) P89LPC9241/9251.
Fig 9.
Interrupt sources, interrupt enables, and power-down wake-up sources
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7.16 I/O ports
The P89LPC9201/9211/922A1/9241/9251 has four I/O ports: Port 0, Port 1 and Port 3. Ports 0 and 1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 9.
Table 9. Number of I/O pins available Reset option Number of I/O pins (28-pin package) 18 17 17 16 16 15
Clock source
On-chip oscillator or watchdog oscillator External clock input
No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported
Low/medium/high speed oscillator (external crystal or resonator)
7.16.1 Port configurations
All but three I/O port pins on the P89LPC9201/9211/922A1/9241/9251 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be configured. 2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open-drain. 7.16.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC9201/9211/922A1/9241/9251 is a 3 V device, but the pins are 5 V tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD.
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An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.3 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9201/9211/922A1/9241/9251 device has high current source on eight pins in push-pull mode. See Table 11 "Limiting values".
7.16.2 Port 0 analog functions
The P89LPC9201/9211/922A1/9241/9251 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.16.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.
* After power-up, all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain. Every output on the P89LPC9201/9211/922A1/9241/9251 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 12 "Static characteristics" for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
7.17 Power monitoring functions
The P89LPC9201/9211/922A1/9241/9251 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.
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7.17.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD FLASH. BOD reset is always on except in total Power-down mode. It could not be disabled in software. BOD interrupt may be enabled or disabled in software. BOD FLASH is always on, except in Power-down modes and could not be disabled in software. BOD reset and BOD interrupt, each has four trip voltage levels. BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are used as trip point configuration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point configuration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD FLASH is used for flash programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9201/9211/922A1/9241/9251 User manual for detail configurations. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage and is negated when VDD rises above the brownout trip voltage. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 12 "Static characteristics" for specifications.
7.17.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
7.18 Power reduction modes
The P89LPC9201/9211/922A1/9241/9251 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.
7.18.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
7.18.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9201/9211/922A1/9241/9251 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.
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Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
7.18.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.
7.19 Reset
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Note: During a power cycle, VDD must fall below VPOR before power is reapplied, in order to ensure a power-on reset (see Table 12 "Static characteristics"). Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1) Power-on detect Brownout detect Watchdog timer Software reset UART break character detect reset
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the
other flag bits are cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set.
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7.19.1 Reset vector
Following reset, the P89LPC9201/9211/922A1/9241/9251 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC9201/9211/922A1/9241/9251 User manual). Otherwise, instructions will be fetched from address 0000H.
7.20 Timers/counters 0 and 1
The P89LPC9201/9211/922A1/9241/9251 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.
7.20.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.20.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.20.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
7.20.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
7.20.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
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7.20.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
7.21 RTC/system timer
The P89LPC9201/9211/922A1/9241/9251 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog reset will reset the RTC and its associated SFRs to the default state. The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers.
7.22 UART
The P89LPC9201/9211/922A1/9241/9251 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9201/9211/922A1/9241/9251 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.22.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
7.22.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 "Baud rate generator and selection").
7.22.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
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7.22.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 "Baud rate generator and selection").
7.22.5 Baud rate generator and selection
The P89LPC9201/9211/922A1/9241/9251 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 10). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generators use OSCCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa897
Fig 10. Baud rate sources for UART (Modes 1, 3)
7.22.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0.
7.22.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.
7.22.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
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8-bit microcontroller with 8-bit ADC
7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.
7.22.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
7.23 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 11. The P89LPC9201/9211/922A1/9241/9251 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
RP
RP
SDA I2C-bus SCL P1.3/SDA P1.2/SCL
P89LPC9201/9211/ 922A1/9241/9251
OTHER DEVICE WITH I2C-BUS INTERFACE
OTHER DEVICE WITH I2C-BUS INTERFACE
002aae430
Fig 11. I2C-bus configuration
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8
ADDRESS REGISTER P1.3
I2ADR
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT 8
CCLK TIMING AND CONTROL LOGIC interrupt
INPUT FILTER P1.2/SCL OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL
SERIAL CLOCK GENERATOR
CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8
status bus
STATUS DECODER
I2STAT
STATUS REGISTER
8
002aaa899
Fig 12. I2C-bus serial interface block diagram
7.24 Analog comparators
Two analog comparators are provided on the P89LPC9201/9211/922A1/9241/9251. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes.
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The overall connections to both comparators are shown in Figure 13. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator's output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFn, after disabling the comparator.
CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) CN1 comparator 1 CO1
change detect
OE1
CMP1 (P0.6)
CMF1
interrupt
change detect
CP2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2 comparator 2
EC
002aae433
Fig 13. Comparator input and output connections
7.24.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V 10 %.
7.24.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
7.24.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.
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If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
7.25 KBI
The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.
7.26 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal 400 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 14 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC9201/9211/922A1/9241/9251 User manual for more details.
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WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH PCLK watchdog oscillator
0 0 1 crystal oscillator 1 XTALWD SHADOW REGISTER /32 PRESCALER 8-BIT DOWN COUNTER reset(1)
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aae015
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 14. Watchdog timer in Watchdog mode (WDTE = 1)
7.27 Additional features
7.27.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
7.27.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
7.28 Flash program memory
7.28.1 General description
The P89LPC9201/9211/922A1/9241/9251 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9201/9211/922A1/9241/9251 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and
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programming mechanisms. The P89LPC9201/9211/922A1/9241/9251 uses VDD as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.
7.28.2 Features
* * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ISP/IAP/ICP. Internal fixed boot ROM, containing low-level IAP routines available to user code. Default loader providing ISP via the serial port, located in upper end of user program memory. memory space, providing flexibility to the user.
* Boot vector allows user-provided flash loader code to reside anywhere in the flash * * * * *
Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 100,000 typical erase/program cycles for each byte. 10 year minimum data retention.
7.28.3 Flash organization
The program memory consists of two/four/eight 1 kB sectors on the P89LPC9201/9211/922A1/9241/9251 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
7.28.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
7.28.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space. Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.
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7.28.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9201/9211/922A1/9241/9251 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9201/9211/922A1/9241/9251 User manual.
7.28.7 IAP
IAP is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The NXP IAP has made in-application programming in an embedded application possible without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to FEFFH, thereby not conflicting with the user program memory space. In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9201/9211/922A1/9241/9251 User manual.
7.28.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9201/9211/922A1/9241/9251 through the serial port. This firmware is provided by NXP and embedded within each P89LPC9201/9211/922A1/9241/9251 device. The NXP ISP facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
7.28.9 Power-on reset code execution
The P89LPC9201/9211/922A1/9241/9251 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC9201/9211/922A1/9241/9251 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H.
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Table 10 shows the factory default Boot Vector setting for these devices. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. This code can be erased by the user. Remark: Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired.
Table 10. Device Default boot vector values and ISP entry points Default boot vector 07H 0FH 1FH Default bootloader entry point 0700H 0F00H 1F00H Default bootloader code range 0600H to 07FFH 0E00H to 0FFFH 1E00H to 1FFFH 1 kB sector range 0400H to 07FFH 0C00H to 0FFFH 1C00H to 1FFFH
P89LPC9201 P89LPC9211/9241 P89LPC922A1/9251
7.28.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC9201/9211/922A1/9241/9251 User manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot vector is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
7.29 User configuration bytes
Some user-configurable features of the P89LPC9201/9211/922A1/9241/9251 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1 and UCFG2. Please see the P89LPC9201/9211/922A1/9241/9251 User manual for additional details.
7.30 User sector security bytes
There are two/four/eight User Sector Security Bytes on the P89LPC9201/9211/922A1/9241/9251. Each byte corresponds to one sector. Please see the P89LPC9201/9211/922A1/9241/9251 User manual for additional details.
8. ADC (P89LPC9241/9251)
8.1 General description
The P89LPC9241/9251 has two analog-to-digital converter modules: ADC0 and ADC1. ADC1 is an 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter. ADC0 is dedicated for on-chip temperature sensor which operates over wide
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temperature. The temperature sensor is measured through Anin03. Anin00, Anin01 and Anin02 are unused. A block diagram of the ADC is shown in Figure 15 "ADC block diagram". The ADC consists of an 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.
8.2 Features
I I I I 8-bit, 4-channel multiplexed input, successive approximation ADC. On-chip wide range temperature sensor. Four result registers for each A/D. Six operating modes: N Fixed channel, single conversion mode. N Fixed channel, continuous conversion mode. N Auto scan, single conversion mode. N Auto scan, continuous conversion mode. N Dual channel, continuous conversion mode. N Single step mode. Three conversion start modes: N Timer triggered start. N Start immediately. N Edge triggered. 8-bit conversion time of 1.61 s at an A/D clock of 8.0 MHz. Interrupt or polled operation. Boundary limits interrupt. DAC output to a port pin with high output impedance. Clock divider. Power-down mode.
I
I I I I I I
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8.3 Block diagram
input MUX Anin00 Anin01 Anin02 Anin03 comp + SAR -
2:1 MUX Vref(bg) Vsen
DAC0
8
AD10 AD11 AD12 AD13
Anin10 Anin11 Anin12 Anin13
input MUX comp + SAR -
CONTROL LOGIC
DAC1
8
CCLK
002aae432
Fig 15. ADC block diagram
8.4 Temperature sensor
An on-chip wide-temperature range temperature sensor is integrated. It provides temperature sensing capability of -40 C ~ 85 C. ADC0 is dedicated for the temperature sensor, and the temperature sensor is measured through Anin03. To get an accurate temperature value, it is necessary to get supply voltage by measuring the internal reference voltage Vref(bg) first. Please see the P89LPC9201/9211/922A1/9241/9251 User manual for detailed usage of temperature sensor.
8.5 ADC operating modes
8.5.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.
8.5.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result register. The user may select whether an interrupt can be generated after every four conversions. Additional conversion results will again cycle through the four result register, overwriting the previous results. Continuous conversions continue until terminated by the user.
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8.5.3 Auto scan, single conversion mode
Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.
8.5.4 Auto scan, continuous conversion mode
Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.
8.5.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).
8.5.6 Single step mode
This special mode allows `single-stepping' in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes.
8.6 Conversion start modes
8.6.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.
8.6.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all ADC operating modes.
8.6.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.
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8.7 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable. An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 bits have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.
8.8 DAC output to a port pin with high output impedance
The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin.
8.9 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.
8.10 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D and temperature sensor do not function. If temperature sensor or the A/D are enabled, they will consume power. Power can be reduced by disabling temperature sensor and A/D.
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9. Limiting values
Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/Otot(max) Vn Ptot(pack) Parameter bias ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total input/output current voltage on any other pin total power dissipation (per package) except VSS, with respect to VDD based on package heat transfer, not device power consumption human body model; all pins charged device model; all pins
[1]
[2]
Conditions
Min -55 -65 -
Max +125 +150 20 20 100 3.5 1.5
Unit C C mA mA mA V W
Vesd
electrostatic discharge voltage
-2000 -500
+2000 +500
V V
The following applies to Table 11: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[2]
system frequency (MHz) 18
12
2.4
2.7
3.0 VDD (V)
3.3
3.6
002aae351
Fig 16. Frequency vs. supply voltage
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8-bit microcontroller with 8-bit ADC
10. Static characteristics
Table 12. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol IDD(oper) IDD(idle) IDD(pd) IDD(tpd) (dV/dt)r VDDR Vth(HL) VIL Vth(LH) VIH Vhys VOL Parameter operating supply current Idle mode supply current Power-down mode supply current total Power-down mode supply current rise rate data retention supply voltage HIGH-LOW threshold voltage LOW-level input voltage LOW-HIGH threshold voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except SCL, SDA SCL, SDA only except SCL, SDA SCL, SDA only port 1 IOL = 20 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z IOL = 3.2 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z VOH HIGH-level output voltage IOH = -20 A; VDD = 2.4 V to 3.6 V; all ports, quasi-bidirectional mode IOH = -3.2 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode IOH = -10 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode Vxtal Vn Ciss IIL ILI ITHL crystal voltage voltage on any other pin input capacitance LOW-level input current input leakage current HIGH-LOW transition current VI = 0.4 V VI = VIL, VIH, or Vth(HL) all ports; VI = 1.5 V at VDD = 3.6 V on XTAL1, XTAL2 pins; with respect to VSS except XTAL1, XTAL2, VDD; with respect to VSS
[7] [6]
Conditions VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V; voltage comparators powered down VDD = 3.6 V of VDD; to ensure POR signal
[2] [2] [3] [3] [4]
Min 5 1.5 0.22VDD -0.5 0.7VDD -
Typ[1] 10 14 3.25 5 20 1 0.4VDD 0.6VDD 0.2VDD 0.6
Max 15 23 5 7 40 5 5000 0.3VDD 0.7VDD 5.5 1.0
Unit mA mA mA mA A A V/S V V V V V V V
[5]
[6]
-
0.2
0.3
V
VDD - 0.3
VDD - 0.2
-
V
VDD - 0.7
VDD - 0.4
-
V
-
3.2
-
V
-0.5 -0.5 -30
-
+4.0 +5.5 15 -80 1 -450
V V pF A A A
[8] [9] [10] [11]
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8-bit microcontroller with 8-bit ADC
Table 12. Static characteristics ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol Parameter Conditions pin RST Min 10 1.11 Typ[1] 1.23 10 Max 30 1.34 20 Unit k V ppm/ C RRST_N(int) internal pull-up resistance on pin RST Vref(bg) TCbg band gap reference voltage band gap temperature coefficient
[1] [2] [3] [4] [5] [6] [7]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper) specification is measured using an external clock with code while(1) {} executed from on-chip flash. The IDD(idle) specification is measured using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. The IDD(pd) specification is measured using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. See Section 9 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode.
[8] [9]
[10] Measured with port in high-impedance mode. [11] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
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10.1 Current characteristics
Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed.
16 IDD (mA) 12
002aae363
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 17. IDD(oper) vs. frequency at +25 C
16 IDD (mA) 12
002aae364
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 18. IDD(oper) vs. frequency at -40 C
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16 IDD (mA) 12
002aae365
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 19. IDD(oper) vs. frequency at +85 C
5.0 IDD (mA) 4.0
002aae366
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: Idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 20. IDD(idle) vs. frequency at +25 C
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5.0 IDD (mA) 4.0
002aae367
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: Idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 21. IDD(idle) vs. frequency at -40 C
5.0 IDD (mA) 4.0
002aae368
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: Idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 22. IDD(idle) vs. frequency at +85 C
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20.0 IDD (A) 18.0
002aae369
(1)
16.0
(2)
14.0
(3)
12.0
10.0 2.4
2.8
3.2 VDD (V)
3.6
Test conditions: Power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. (1) +85 C (2) +25 C (3) -40 C
Fig 23. IDD(pd) vs. VDD
1.2 IDD (A) 0.8
002aae370
(1)
0.4
(2)
(3)
0.0 2.4
2.8
3.2 VDD (V)
3.6
Test conditions: Total Power-down mode, using internal RC oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. (1) +85 C (2) -40 C (3) +25 C
Fig 24. IDD(tpd) vs. VDD
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10.2 Internal RC/watchdog oscillator characteristics
Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed.
0.2 frequency deviation (%) 0.1
002aae344
0
-0.1
-0.2 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of internal RC oscillator = 7.3728 MHz
Fig 25. Average internal RC oscillator frequency vs. VDD at +25 C
0.2 frequency deviation (%) 0.1
002aae346
0
-0.1
-0.2 2.4
2.8
3.2 VDD (V)
3.6
Note: Central frequency of internal RC oscillator = 7.3728 MHz
Fig 26. Average internal RC oscillator frequency vs. VDD at -40 C
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0.2 frequency deviation (%) 0
002aae347
-0.2
-0.4
-0.6 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of internal RC oscillator = 7.3728 MHz
Fig 27. Average internal RC oscillator frequency vs. VDD at +85 C
2.5 frequency deviation (%) 1.5
002aae348
0.5
-0.5
-1.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 kHz
Fig 28. Average watchdog oscillator frequency vs. VDD at +25 C
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0.5 frequency deviation (%) -0.5
002aae349
-1.5
-2.5
-3.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 kHz
Fig 29. Average watchdog oscillator frequency vs. VDD at -40 C
1.5 frequency deviation (%) 0.5
002aae350
-0.5
-1.5
-2.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 kHz
Fig 30. Average watchdog oscillator frequency vs. VDD at +85 C
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10.3 BOD characteristics
Table 13. BOD static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol Vtrip Parameter trip voltage Conditions falling stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 BOICFG1, BOICFG0 = 11 rising stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 BOICFG1, BOICFG0 = 11 BOD reset Vtrip trip voltage falling stage BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 rising stage BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 BOD EEPROM/FLASH Vtrip trip voltage falling stage rising stage
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
Min
Typ[1]
Max
Unit
BOD interrupt 2.25 2.60 3.10 2.30 2.70 3.15 2.55 2.80 3.40 2.60 2.90 3.45 V V V V V V
2.10 2.25 2.80 2.20 2.30 2.90 2.25 2.30
-
2.30 2.55 3.20 2.40 2.60 3.30 2.55 2.60
V V V V V V V V
VDD Vtrip (BOF/BOIF set by hardware) (BOF/BOIF can be cleared in software)
BOF/BOIF
002aae352
Fig 31. BOD interrupt/reset characteristics
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11. Dynamic characteristics
Table 14. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON, VDD = 2.7 V to 3.6 V fosc(WD) fosc Tcy(clk) fCLKLP Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time see Figure 33 see Figure 33 see Figure 33 see Figure 33 see Figure 32 see Figure 32 see Figure 32 see Figure 32 see Figure 32 33 33 16Tcy(clk) 13Tcy(clk) 150 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 8 8 Tcy(clk) + 20 0 33 33 1333 1083 150 8 8 103 0 ns ns ns ns ns ns ns ns ns 125 50 50 15 125 50 50 15 ns ns ns ns internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency see Figure 33 Tamb = 25 C Variable clock Min 7.189 Max 7.557 fosc = 12 MHz Min 7.189 Max 7.557 MHz Unit
14.378
15.114
14.378 15.114 MHz
380 0 83 0
420 12 8
380 -
420 -
kHz MHz ns MHz
Shift register (UART mode 0)
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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Table 15. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON fosc(WD) fosc Tcy(clk) fCLKLP internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST tsa P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time see Figure 33 see Figure 33 see Figure 33 see Figure 33 see Figure 32 see Figure 32 see Figure 32 see Figure 32 see Figure 32 22 22 16Tcy(clk) 13Tcy(clk) 150 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 5 5 Tcy(clk) + 20 0 22 22 888 722 150 5 5 75 0 ns ns ns ns ns ns ns ns ns see Figure 33 Tamb = 25 C Variable clock Min 7.189 Max 7.557 fosc = 18 MHz Min 7.189 Max 7.557 MHz Unit
14.378 380 0 55 0
15.114 420 18 8
14.378 15.114 MHz 380 420 kHz MHz ns MHz
Glitch filter tgr 125 50 50 15 125 50 50 15 ns ns ns ns
Shift register (UART mode 0)
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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11.1 Waveforms
TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 32. Shift register mode timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 33. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
11.2 ISP entry mode
Table 16. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol tVR tRH tRL Parameter RST HIGH time RST LOW time Conditions pin RST pin RST Min 50 1 1 Typ Max 32 Unit s s s VDD active to RST active delay time pin RST
VDD tVR RST tRL
002aaa912
tRH
Fig 34. ISP entry waveform
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12. Other characteristics
12.1 Comparator electrical characteristics
Table 17. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 20 VDD - 0.3 -50 500 10 10
Unit mV V dB ns s A
-
0 V < VI < VDD
-
This parameter is characterized, but not tested in production.
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12.2 ADC/temperature sensor electrical characteristics
Table 18. ADC/temperature sensor electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. All limits valid for an external source impedance of less than 10 k. Symbol VDDA(ADC) VSSA VIA Cia ED EL(adj) EO EG Eu(tot) MCTC ct(port) SRin Tcy(ADC) tADC Vsen TC tstartup Parameter ADC analog supply voltage analog ground voltage analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate ADC clock cycle time ADC conversion time sensor voltage temperature coefficient start-up time ADC enabled Tamb = +0 C 0 kHz to 100 kHz VSS - 0.2 111 890 11.3 200 VDD + 0.2 15 1 1 2 1 2 1 -60 100 2000 13Tcy(ADC) Conditions Min Typ Max Unit V V V pF LSB LSB LSB % LSB LSB dB V/ms ns s mV mV/C s
Temperature sensor
start trigger
adc_clk
1
2
3
4
5
6
7
8
9
10
11
12
13
clk
serial_data_out
D7
D6
D5
D4
D3
D2
D1
D0
ADCDATA_REG
ADCDATA
002aae371
Fig 35. ADC conversion timing
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offset error EO 255
gain error EG
254
253
252
(2)
7 code out 6
(1)
5
4
3
2
1
1 LSB (ideal) 253 254 255 256
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB =
VDDA - VSSA 256
002aae372
(1) Example of an actual transfer curve. (2) The ideal transfer curve.
Fig 36. ADC characteristics
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13. Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 37. TSSOP20 package outline (SOT360-1)
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8-bit microcontroller with 8-bit ADC
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.1
e1 7.62 0.3
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 JEITA SC-603 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 38. DIP20 package outline (SOT146-1)
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14. Abbreviations
Table 19. Acronym ADC BOD CPU CRC DAC EPROM EEPROM EMI PLL PWM RAM RC RTC SAR SFR UART WDT Abbreviations Description Analog-to-Digital Converter Brownout Detection Central Processing Unit Cyclic Redundancy Check Digital-to-Analog Converter Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory Electro-Magnetic Interference Phase-Locked Loop Pulse-Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Universal Asynchronous Receiver/Transmitter WatchDog Time
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15. Revision history
Table 20. Revision history Release date 20090416 Data sheet status Preliminary data sheet Change notice Supersedes Document ID P89LPC92X_1
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 16 April 2009
72 of 74
www..com
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 Special function registers . . . . . . . . . . . . . . . . 12 7.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 26 7.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 26 7.4 Crystal oscillator option . . . . . . . . . . . . . . . . . 26 7.4.1 Low speed oscillator option . . . . . . . . . . . . . . 26 7.4.2 Medium speed oscillator option . . . . . . . . . . . 26 7.4.3 High speed oscillator option . . . . . . . . . . . . . . 26 7.5 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 On-chip RC oscillator option . . . . . . . . . . . . . . 27 7.7 Watchdog oscillator option . . . . . . . . . . . . . . . 27 7.8 External clock input option . . . . . . . . . . . . . . . 27 7.9 Clock sources switch on the fly. . . . . . . . . . . . 27 7.10 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 28 7.11 CCLK modification: DIVM register . . . . . . . . . 28 7.12 Low power select . . . . . . . . . . . . . . . . . . . . . . 28 7.13 Memory organization . . . . . . . . . . . . . . . . . . . 29 7.14 Data RAM arrangement . . . . . . . . . . . . . . . . . 29 7.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.15.1 External interrupt inputs . . . . . . . . . . . . . . . . . 30 7.16 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.16.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 32 7.16.1.1 Quasi-bidirectional output configuration . . . . . 32 7.16.1.2 Open-drain output configuration . . . . . . . . . . . 32 7.16.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 33 7.16.1.4 Push-pull output configuration . . . . . . . . . . . . 33 7.16.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 33 7.16.3 Additional port features. . . . . . . . . . . . . . . . . . 33 7.17 Power monitoring functions. . . . . . . . . . . . . . . 33 7.17.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 34 7.17.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . 34 7.18 Power reduction modes . . . . . . . . . . . . . . . . . 34 7.18.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.18.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 34 7.18.3 7.19 7.19.1 7.20 7.20.1 7.20.2 7.20.3 7.20.4 7.20.5 7.20.6 7.21 7.22 7.22.1 7.22.2 7.22.3 7.22.4 7.22.5 7.22.6 7.22.7 7.22.8 7.22.9 7.22.10 7.23 7.24 7.24.1 7.24.2 7.24.3 7.25 7.26 7.27 7.27.1 7.27.2 7.28 7.28.1 7.28.2 7.28.3 7.28.4 7.28.5 7.28.6 7.28.7 7.28.8 7.28.9 7.28.10 7.29 7.30 8 Total Power-down mode . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . Timers/counters 0 and 1 . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Using flash as data storage . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on reset code execution . . . . . . . . . . . Hardware activation of the bootloader . . . . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . ADC (P89LPC9241/9251). . . . . . . . . . . . . . . . . 35 35 36 36 36 36 36 36 36 37 37 37 37 37 37 38 38 38 38 38 39 39 39 40 41 41 41 42 42 43 43 43 43 43 44 44 44 44 45 45 45 45 46 46 46 46
continued >>
P89LPC92X1_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 16 April 2009
73 of 74
www..com
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
46 47 48 48 48 48 48 49 49 49 49 49 49 49 49 50 50 50 50 51 52 54 58 61 62 64 64 65 65 66 68 70 71 72 72 72 72 72 72 73
8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.6.1 8.6.2 8.6.3 8.7 8.8 8.9 8.10 9 10 10.1 10.2 10.3 11 11.1 11.2 12 12.1 12.2 13 14 15 16 16.1 16.2 16.3 16.4 17 18
General description. . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . Temperature sensor . . . . . . . . . . . . . . . . . . . . ADC operating modes . . . . . . . . . . . . . . . . . . Fixed channel, single conversion mode . . . . . Fixed channel, continuous conversion mode . Auto scan, single conversion mode . . . . . . . . Auto scan, continuous conversion mode . . . . Dual channel, continuous conversion mode . . Single step mode . . . . . . . . . . . . . . . . . . . . . . Conversion start modes . . . . . . . . . . . . . . . . . Timer triggered start . . . . . . . . . . . . . . . . . . . . Start immediately . . . . . . . . . . . . . . . . . . . . . . Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . Boundary limits interrupt. . . . . . . . . . . . . . . . . DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down and Idle mode . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Current characteristics . . . . . . . . . . . . . . . . . . Internal RC/watchdog oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . BOD characteristics . . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . ADC/temperature sensor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 April 2009 Document identifier: P89LPC92X1_1

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